1. Field of the Invention
The present invention relates to a testing device which checks operations of a synchronous-transfer-mode switch provided in a switch board.
2. Description of the Related Art
FIG. 1 is an illustrative drawing showing a synchronous-transfer-mode (STM) switch having 4 input links and 4 output links as an example of an STM switch.
As shown in the figure, the STM switch has 4 input links #0 through #3 and 4 output links #0 through #3. Each link has a time-division-multiplexing signal passing therethrough, each frame of which is comprised of 1024 time slots TS0 through TS1023. At the beginning of each frame, a frame clock FCK exhibits a pulse as a frame-synchronization signal.
FIG. 2 is an illustrative drawing showing a configuration of the STM switch of FIG. 1.
As shown in the figure, a plurality of STM switches are provided, each corresponding to a respective one of the output links #0 through #3. Each of the STM switches receives all the input links #0 through #3 on the input side thereof. Each STM switch includes a time-switch memory and a control switch memory. The time-switch memory can store data as much as for 4096 time slots, which corresponds to the number of time slots of all the input links #0 through #3. The control memory can store setting data as much as of 1024 different types, which corresponds to the capacity of the output link (i.e., 1024 time slots). The setting data stored in the control memory is supplied from a system-control unit (now shown) situated on the call-control-system side. In the STM switch of FIG. 2, time switching is conducted by use of the time-switch memory and the control memory. This technology is well within the scope of ordinary skill in the art, and a description thereof will be omitted.
When there is a need to conduct a test with regard to operations of the STM switch, the STM switch may be configured in the manner as shown in FIG. 3. Namely, a test data sending block (TDSB) 2 is provided on the input link #0, and a test data receiving block (TDRB) 3 is provided on the output link #0. Further, a loop-back block 4 is provided for the purpose of feeding back a signal from the output link #3 to the input link #3.
The test data sending block 2, responsive to an instruction from the system-control unit (not shown: comprised of software relating to a call-process system), stores test data in time slots of the input link #0, thereby supplying the test data to an STM switch 1.
The test data receiving block 3 has a capacity to store all the data of all the time slots TS0 through TS1023 supplied from the STM switch 1 to the output link #0. The system-control unit can read data of any time slot stored in the test data receiving block 3.
Further, the loop-back block 4 has a function to connect the output link #3 of the STM switch 1 to the input link #3.
FIG. 4 is an illustrative drawing showing a phase relation between an input link and an output link. As shown in FIG. 4, generally, the input and output of the STM switch 1 have different phases. In this example, a time slot TS0 of the input link has a phase difference of xxcfx84 relative to a time slot TS0 of the output link. The loop-back block 4 receives data of all the time slots of the output link #3, and supplies them to the input link #3 after absorbing all the phase differences. As schematically shown in the figure, a time slot TSxcex1 of the output link #3 is positioned on the feedback path such that it coincides with the same time slot TSxcex1 of the input link #3.
FIG. 5 is an illustrative drawing for explaining a test of switching operations of the STM switch by using the test system of FIG. 3. The following is the test sequence to be followed.
1) The system-control unit instructs the test data sending block 2 to store a test data pattern A in a time slot TSxcex1 and supply it to the STM switch 1.
2) The system-control unit instructs the STM switch 1 (to be exact, the control memory in the STM switch 1 corresponding to the output link #3) that the time slot TSxcex1 of the input link #0 be supplied as the a time slot TSxcex2 of the output link #3 via switching operations.
3) The system-control unit instructs the STM switch 1 (to be exact, the control memory in the STM switch 1 corresponding to the output link #0) that a time slot TSxcex2 of the input link #3 be supplied as the a time slot TSxcex93 of the output link #0 via switching operations.
4) Because of the process of 1), the test data sending block 2 supplies the test data pattern A to the STM switch 1 as the time slot TSxcex1 of the input link #.
5) Because of the process of 2), the test data pattern A is output from the STM switch 1 as the time slot TSxcex2 of the output link #3.
6) The test data pattern A is then supplied to the loop-back block 4, and is thereafter input to the STM switch 1 as the time slot TSxcex2 of the input link #3.
7) Because of the process of 3), the test data pattern A is output from the STM switch 1 as the time slot TSxcex93 of the output link #.
8) The test data pattern A is then stored in the test data receiving block 3 of the output link #0 as the time slot TSxcex93.
9) The system-control unit instructs the test data receiving block 3 to output the data of the time slot TSxcex93.
10) In response to this instruction, the test data receiving block 3 outputs the test data pattern A to the system-control unit.
11) The system control unit compares the test data pattern A obtained at the step 10) with the test data pattern A used at the step 1).
12) If there is a match at the step 11), the test is indicating perfectly normal operations. Otherwise, the test is indicating abnormal operations.
The test of switching operations and the configuration for the test as described above have the following problems.
a) As can be seen from the above description, the test of switching operations can check the connection between the input link #0 to the output link #3 as well as the connection between the input link #3 and the output link #0. However, no test can be conducted with respect to other connections between the input links and the output links.
b) In the related-art test system, each of the test data sending block 2 and the test data receiving block 3 takes up one link (the input link #0 and the output link #0, respectively, in the above example). Another link is used for the loop-back purpose (the input link #3 and the output link #3 in the above example). In this configuration, only two links (the input links #1 and #2 and the output links #1 and #2) are remaining as available for practical use. That is, only half the total links are available.
Accordingly, there is a need for a test of switching operations which can check operations with respect to any routes (connections) between the input links and the output links without reducing the number of links available for practical use.
Accordingly, it is a general object of the present invention to provide a device for testing switching operations which can satisfy the need described above.
It is another and more specific object of the present invention to provide a device for testing switching operations which can check operations with respect to any routes (connections) between the input links and the output links without reducing the number of links available for practical use.
In order to achieve the above objects according to the present invention, a device for testing a synchronous-transfer-mode switch which is connected to a plurality of input links and a plurality of output links includes a plurality of test data sending blocks each provided for a corresponding one of the input links and each equipped with a function to set test data in a particular time slot of the corresponding one of the input links, thereby allowing the corresponding one of the input links to convey time slots used for a non-test purpose as well as the particular time slot used for a test, and a plurality of test data receiving blocks each provided for a corresponding one of the output links and each equipped with a function to store data of time slots of the corresponding one of the output links when the time slots of the corresponding one of the output links are used for the test.
In the device described above, a test data sending block can store the test data in any time slot of any input link, and the test data is then extracted from the time slot by a test data receiving block after the time slot containing the test data is switched by the STM switch to be supplied to the test data receiving block. This makes it possible to test the path connecting the test data sending block and the test data receiving block.
In this device, the test data sending blocks and the test data receiving blocks are allocated to each of the existing links, thereby making it possible to test any connections between the input links and the output links.
Further, since no links are dedicated for the sake of the test, the number of links available for practical purposes is not decreased, contrasting to the related art where the number is decreased because some of the links are dedicated for the test use.
According to one aspect of the present invention, the device as described above is such that said test data sending blocks select the particular time slot based on instruction sent from a call-process system.
According to another aspect of the present invention, the device as first described is such that said test data sending blocks select the particular time slot based on instruction sent from one of hardware and software provided on a side of a speech-path system.
According to another aspect of the present invention, the device as first described further includes a table, provided on a side of a speech-path system, which stores a used/unused status of each time slot with respect to each of the input links, the used/unused status of each time slot being updated based on a notice sent from a call-process system, wherein said test data sending blocks select the particular time slot based on said table.
According to another aspect of the present invention, the device as first described further includes a control memory and a time-switch memory, provided with respect to each one of the output links on a side of a speech-path system, said control memory storing write addresses of said time-switch memory at which time slots of the corresponding input links are stored, wherein said control memory includes an additional bit for indicating the used/unused status of the time slots, the used/unused status of each time slot being updated based on a notice sent from a call-process system, wherein said test data sending blocks select the particular time slot based on the additional bit of said control memory.
According to another aspect of the present invention, the device as first described further includes a control memory and a time-switch memory, provided with respect to each one of the output links on a side of a speech-path system, said control memory storing write addresses of said time-switch memory at which time slots of the input links are stored, wherein said control memory stores a specific pattern if a corresponding time slot is an unused time slot, thereby indicating a used/unused status of each time slot, the used/unused status of each time slot being updated based on a notice sent from a call-process system, and wherein said test data sending blocks select the particular time slot based on the used/unused status indicated by said control memory.
According to another aspect of the present invention, the device as first described is such that each of said test data sending blocks includes a register which stores a used/unused status of each time slot with respect to a corresponding one of the input links, each of said test data sending blocks selecting the particular time slot based on the used/unused status stored in said register.
According to another aspect of the present invention, the device as first described further includes a supervising device controlling said test data sending blocks and including a register which stores a used/unused status of each time slot with respect to each of the input links, each of said test data sending blocks selecting the particular time slot based on the used/unused status stored in said register.
According to another aspect of the present invention, the device as first described is such that said test data receiving blocks select time slots having the test data stored therein based on instruction sent from a call-process system, and store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described is such that said test data receiving blocks select time slots having the test data stored therein based on instruction sent from one of hardware and software provided on a side of a speech-path system, and store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described further includes a table, provided on a side of a speech-path system, which stores a used/unused status of each time slot with respect to each of the output links, the used/unused status of each time slot being updated based on a notice sent from a call-process system, wherein said test data receiving blocks select time slots having the test data stored therein based on said table, and store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described further includes a control memory and a time-switch memory, provided with respect to each one of the output links on a side of a speech-path system, said control memory storing write addresses of said time-switch memory at which time slots of the corresponding input links are stored, wherein said control memory includes an additional bit for indicating the used/unused status of the time slots, the used/unused status of each time slot being updated based on a notice sent from a call-process system, wherein said test data receiving blocks select time slots having the test data stored therein based on the additional bit of said control memory, and store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described further includes a control memory and a time-switch memory, provided with respect to each one of the output links on a side of a speech-path system, said control memory storing write addresses of said time-switch memory at which time slots of the input links are stored, wherein said control memory stores a specific pattern if a corresponding time slot is an unused time slot, thereby indicating a used/unused status of each time slot, the used/unused status of each time slot being updated based on a notice sent from a call-process system, and wherein said test data receiving blocks select time slots having the test data stored therein based on the used/unused status indicated by said control memory, and store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described is such that each of said test data receiving blocks includes a register which stores a used/unused status of each time slot with respect to a corresponding one of the output links, each of said test data receiving blocks selecting time slots having the test data stored therein based on the used/unused status stored in said register so as to store the test data of the selected time slots.
According to another aspect of the present invention, the device as first described further includes a supervising device controlling said test data receiving blocks and including a register which stores a used/unused status of each time slot with respect to each of the output links, each of said test data receiving blocks selecting time slots having the test data stored therein based on the used/unused status stored in said register so as to store the test data of the selected time slots.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.